1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the semiconductor memory, and more particularly, to a structure of a semiconductor memory device having a trench capacitor in a memory cell and a method of manufacturing the semiconductor memory.
2. Description of the Related Art
The integration level of a semiconductor integrated circuit has been increased year by year. This tendency is remarkably observed in a dynamic random access memory (DRAM). To increase the integration level of a DRAM cell having a single transistor and a single capacitor, the size of each part must be reduced. As a DRAM cell is reduced in size, a wiring layer connecting a source diffusion layer (or drain diffusion layer) of a transistor and a capacitor electrode is also reduced in area and width. As a result, it becomes difficult for the DRAM cell to maintain requisite electrical characteristics.
Now, the structure of a DRAM having a trench capacitor will be described by way of example. FIG. 9 is a sectional view showing the essential portion of a conventional DRAM. A semiconductor substrate 30 has a trench 31 formed therein. Around the lower portion of the trench 31 within the semiconductor substrate 30, a plate electrode 32 of an N-type diffusion layer is formed as a capacitor electrode. On the lower inner surface of the trench 31, an NO film 33 (formed of a silicon nitride film and a silicon oxide film) serving as a dielectric film of a capacitor is formed.
Inside the NO film 33 of the trench 31, a polysilicon layer 34 serving as an upper electrode of the capacitor is formed. On the polysilicon layer 34 and along the inner surface of the trench, a collar oxide film 35 is formed to separate a transistor region to be formed in the semiconductor substrate 30 and a storage node of the trench capacitor. Inside the collar oxide film 35 of the trench 31, a polysilicon layer 36 serving as a wiring layer is formed in contact with the polysilicon layer 34.
On the polysilicon layer 36, a buried strap (BS) contact layer 37 serving as a contact layer connecting between the source diffusion layer 17 of a memory-cell transistor and the polysilicon layer 36 is formed. The BS contact layer 37 is buried in the trench until it is flush with the surface of the semiconductor substrate 30.
On the semiconductor substrate 30, a gate electrode 14 is formed with a gate insulating film 13 interposed between them. Around the gate electrode 14, a gate cap insulating film 15 is formed so as to cover the gate electrode 14. On both side surfaces of the gate cap insulating film 15, a gate sidewall insulating film 16 is formed. A source diffusion layer 17 and a drain diffusion layer 18 are formed in the semiconductor substrate 1 underneath both sides of the gate electrode 14, respectively.
In the DRAM thus constructed, when a BS contact is formed, usually a frontage of about 1200 to 1500 Å (more specifically, the depth of the BS contact in contact with a side surface of the active area in which the memory cell transistor is to be formed) is maintained. However, as the size of the DRAM cell is reduced, it becomes difficult to suppress the punch through caused by impurities diffused from the BS contact layer to the source diffusion layer 17. Furthermore, as the cell size is reduced, the volume of the BS contact layer or the frontage of the BS contact layer decreases, with the result that the resistance value of the BS contact layer increases.
As one of solutions to these problems, it may be considered to employ a surface strap (SS) contact, which is a strap contact layer formed on the surface of the semiconductor substrate. However, when the SS contact layer is formed, a trench top oxide (TTO) film formed on the top of a trench capacitor must be etched back to expose the polysilicon layer 36 serving as a wiring layer. In the etching-back step, the collar oxide film formed on the sidewall of a trench is inevitably etched at the same time. When the SS contact layer is formed by burying, for example, polysilicon, a recess formed in the sidewall of the trench is not sufficiently buried with the polysilicon, with the result that a void and the like may be produced. When a void is formed, a film may be peeled off or the resistance value of the BS contact layer may be increased.
When the SS contact layer is formed not by burying polysilicon but by the epitaxial growth of silicon, a recess of sidewall of a trench may not be sufficiently bridged by the growth of silicon crystal, or alternatively, the silicon substrate or a polysilicon layer is deformed by migration of the crystal when a native oxide film is removed by hydrogen annealing.
As a relevant technique, it has been proposed to form an analogous structure to a DRAM without increasing the area by employing a gain cell having a trench structure (refer to Japanese Patent Application KOKAI No. 2002-118240).